Aehr Test Systems (AEHR) Q4 FY26 earnings call: guidance and Q&A

What is the assumed product mix for the $130M-$150M FY27 revenue guidance, specifically for AI chips, silicon photonics, power, and memory?

Gayn Erickson stated the mix is expected to be similar to last year: AI around 70%, silicon photonics 15-20%, and power semiconductor/miscellaneous for the rest. No memory revenue is anticipated in the current guidance, and revenue from the new benchmark customer would be upside.

“AI is going to be a big chunk of our business this year, both in dollars and percentage.”

asked by Christian Schwab · answered by Gayn Erickson

Are you more confident in securing memory orders in FY27 for revenue in FY28, given previous similar statements?

Gayn Erickson expressed continued confidence, noting more detailed work has begun, including hiring and architectural assessments. He highlighted the impact of high-bandwidth flash and new HBM standards with embedded BIST capabilities as potential accelerators for HBM adoption, but still cautioned against modeling significant memory revenue for next year.

“It's given me some additional optimism with respect to our ability to maybe do HBM sooner than we were thinking certainly 6 months ago.”

asked by Christian Schwab · answered by Gayn Erickson

What is the company's current top-line revenue capacity, considering recent expansions?

Gayn Erickson explained that the Fremont facility's capacity has increased tenfold, capable of producing approximately 20 combined package or wafer-level systems per month. Additionally, the new Southeast Asia contract manufacturer can produce over 20 Sonoma systems per month. He estimated the total capacity to be in the hundreds of millions of dollars, emphasizing flexibility to handle lumpy demand without excessive fixed infrastructure.

“Our capacity is significant. I mean, measured in hundreds of millions of dollars for sure.”

asked by Christian Schwab · answered by Gayn Erickson

Is the 20 Sonoma systems per month capacity from the Southeast Asia CM for the larger 'Sonoma Max' systems, and how does that relate to the $140M midpoint guidance?

Gayn Erickson clarified that the production Sonoma systems in backlog are smaller configurations, priced around $600,000-$700,000 apiece, not the larger 'Ultras' (Sonoma Max). He noted that the total package-level burn-in Sonoma revenues are around $50 million, with the bulk of shipments expected in Q2 FY27.

“The production Sonoma systems that we have in backlog, we've shared this with different people, including the consumable elements are somewhere in the $600,000, $700,000 apiece.”

asked by Jed Dorsheimer · answered by Gayn Erickson

Can you update on the discussions with your largest AI processor customer regarding wafer-level burn-in, given their current use of package-level?

Gayn Erickson explained that the lead hyperscaler customer currently uses Sonoma for package-level production for their first and second devices. For a third, future device (not in this fiscal year), they are actively considering wafer-level burn-in due to the significant yield advantage as the number of compute chips per package increases, making package-level burn-in too expensive if one chip fails.

“If you fail one of the compute chips, you throw away the other compute chips and all of the memory. And so at that point, it gets extremely expensive from a yield loss to continue to do package-level burn-in.”

asked by Jed Dorsheimer · answered by Gayn Erickson

How do you view market adoption and your role in GaN, given its reliability challenges, and silicon photonics/co-packaged optics?

Gayn Erickson stated that GaN, despite its diverse applications, consistently requires production burn-in to meet reliability needs, and Aehr has debugged and validated wafer-level burn-in for it. For silicon photonics, the burn-in requirements are clear and central for data centers. He emphasized that burn-in, particularly wafer-level, is currently the fastest-growing segment in semiconductor test.

“I believe that burn-in is by far the fastest-growing segment in all of semiconductor test right now and wafer-level burn-in in particular.”

asked by Jed Dorsheimer · answered by Gayn Erickson

How should investors think about the revenue flow throughout FY27, given the significant year-over-year uplift?

Chris Siu and Gayn Erickson indicated that Q2 FY27 is expected to be a very strong quarter due to significant shipments of package-level Sonoma systems. This could lead to the first half of FY27 being similar to or even better than the second half, a deviation from historical patterns where the second half is typically stronger.

“So there's a high likelihood that the first half might be the same or even better than the second half, but second quarter is going to be a good -- very strong quarter for us.”

asked by Jed Dorsheimer · answered by Chris Siu

Was the $41 million April order for Sonoma systems from the lead hyperscaler, and are they a different customer than the one evaluating wafer-level burn-in?

Gayn Erickson confirmed the $41 million order was for Sonoma systems for the lead hyperscaler, who is currently using package-level burn-in. He clarified that this same customer is also considering wafer-level burn-in for a *third* device, indicating a potential future transition or mixed approach.

“No, that's the one we're talking about that is currently on package. Then the second part is package and the third part is wafer-level or potentially being evaluated for wafer-level.”

asked by Maxwell Michaelis · answered by Gayn Erickson

Does the FY27 guidance include significant revenue from the major AI processor supplier that just completed benchmark testing?

Gayn Erickson stated that revenue from this particular potential customer is 'little to none' in the current FY27 guidance, implying it represents a potential significant upside if orders materialize.

“Let's call it little to none at this point. It's in the noise level.”

asked by Larry Chlebina · answered by Gayn Erickson

Are you engaged with multiple HBM suppliers, and how far along are these discussions?

Gayn Erickson confirmed specific conversations with 2-3 flash memory suppliers and 2 DRAM (HBM) suppliers. He noted that the new HBM standards with logic interfaces for testability are challenging existing memory testers, potentially creating an opportunity for Aehr's logic-tester-like architecture.

“This new HBM has a logic interface for its testability, it's breaking the memory testers.”

asked by Larry Chlebina · answered by Gayn Erickson